As technology scales, modern digital system design has evolved where large systems reside within a single chip (system-on-chip). This significantly increases the complexity of the resources (inter-connect) used for communication between different modules within the system-on-chip (SoC). Further, it adds to the NRE costs of development and the time to design, develop and test the interconnect increases the time to market for the products. This projects plans to develop a generic framework which will generate an optimized application specific Network On chip (NOC) design to be used as the inter-connect for FPGA and ASIC based SoCs. The framework will generate the optimized NOC based on application specifications and design constraints such as low power and low area. The optimized NOC design generated by the framework will be usable in wide range of applications including communication, multimedia and networking SoCs. The framework results will be implemented and tested on a FPGA.