CASE
 
Dr. Shoab A. Khan

Dr. S. A. Khan Dr. Khan’s areas of specialization are Digital Signal Processing, Digital Design and Communication System. He has authored or co-authored more 65 publications in journals and conferences.

Educational Qualifications

Dr. Khan has Ph.D. in Electrical and Computer Engineering from Georgia Institute of Technology; Atlanta, GA. Analog Devices funded his Ph.D. on a project for MIT Lincoln Lab, which involved 64 SHARC DSPs based Mesh for parallel processing application.
He obtained his B.Sc. in Electrical Engineering from UET, Lahore

Work Experience

He has 12+ years industrial experience in companies like Scientific Atlanta, Picture Tel, and Cisco Systems. Mostly he worked on multi-DSP-based systems. As head of R&D group at Communications Enabling Technologies, he headed the team that executed a pioneering work of System on Chip (SoC) design. The team designed the world highest density media processor for carrier class voice processing system. The SoC can handle 2000 calls of G.711 or 624 calls of G.729a with line echo cancellation, voice activity detection, and comfort noise generation. SoC has 40 DSPs with embedded silicon RTOS taking care of the scheduling of different voice channels on these DSPs. A system based on this chip is installed in PTCL 17-enquiry exchange in Peshawar, Pakistan. He is one of the five recipients of National Education Award 2001 in the category of "Outstanding Services to Science and Technology".

Research Publications
S. Khan and V. Madisetti, Signal and Image Processing in C on a Mesh-Based SIMD Supercomputer, Copyright Analog Devices Inc.
S. Khan and V. Madisetti, Yield-based partitioning strategies for MCM and ASEM Design, in Proceedings IEEE Multi-Chip Module Conference, pp. 144-149, 1994, USA.
S. Khan and V. Madisetti, Parallel mapping of back propagation algorithm for mesh signal processor, in IEEE Workshop on Neural Networks for Signal Processing (NNSP'95), September 95, USA
S. Khan and V. Madisetti, High performance signal processing on DSP-based Multiprocessors, in International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'95), November 95, USA
S. Khan and V. Madisetti, System partitioning for MCMs for low power, IEEE Design and Test, pp. 41--52, Vol 12, March 1995, USA
M. Sadiq and S. Khan, Optimal mapping of DSP algorithm onto a VLIW Architecture, in Proc. 1st Comsats National Conference on Mathematical molding 1997.
M. Sadiq and S. Khan, Hardware/Software codesign of application specific signal processing systems, proc. in INMIC’98 Conference, pp. 140, November 1998.
K. Iqbal and S. Khan, Parallel Mapping of Hopfield Neural Networks on an SIMD Super Computer, proc. in INMIC’98 Conference, pp. 141, November 1998.
D. Habib and S. Khan, Parallel mapping of digital signal processing algorithms on a VLIW architecture, in Proc INMIC’98 Conference, pp. 7-11, November 1998.
J. Sultan, S. Khan, S. Aziz and A. Baig, Verification and Design Environment for Timing & Phase Recovery in a Satellite Burst Demodulator, in Proc. INMIC’98 Conference, pp. 38-43, November 1998.
S. Ahsan, M. Saqib and S. Khan, Design and implementation of FEC encoders and decoders for wireless & satellite data transmission applications, in Proc INMIC’98 Conference, pp. 2-6, November 1998.
M. Khan, H. Farooq and S. Khan, Hardware Software Implementation of Direct Digital Frequency Synthesizer, in Proc. INMIC’98 Conference, pp. 32-37, November 1998.
M. Khan, H. Farooq and S. Khan, Digital design of a universal modulator, in Proc. IEEE Fast’98.
D. Habib and S. Khan, VLIW architecture in high rate digital communication, in Proc. IEEE Fast’98.
A. Nadeem and S. Khan, “Four Dimensional Trellis-Coded-Modulation,” in Proc. IEEE Fast’98.
S. A. Khan, S.M. Farhan and M. S. Sadiq, Optimal Time-Shared Design of Digital Signal Processing Architectures, Proceedings INMIC 2000, 2000, p 1-5.
H. Farooq, N. A. Shah, R. Hameed, S. A. Khan and M. S. Khan, Hardware CORDIC Assist to a DSP Processor, Proceedings INMIC 2000, 2000, p 6-9.
Z. Ahmed and S. A. Khan, Development of A Programmable Multiplierless Viterbi Accelerator, Proceedings INMIC 2000, 2000, p 15-18.
M. S. Sadiq and S. A. Khan, Optimal Design & Implementation of CSD Fir Filter, Proceedings INMIC 2000, 2000, p 19-22.
K. Mahmood and S. A. Khan, Optimal Digital Design of Signal Processing Applications using Hybrid Architectures, Proceedings INMIC 2000, 2000, p 48-51.
K. Tanvir and S. A. Khan, Hardware Implementation of Discrete Time Wavelet Transforms Using Recirculating Polyphase Decimation Filter Architecture for A 3-Level Tree Structured QMF Bank, Proceedings INMIC 2000, 2000, p 52-55.
M. Alam and S. A. Khan, VLSI Implementation of Pipelined IIR Digital Filters, Proceedings INMIC 2000, 2000, p 56-61.
R. Mehmoob and S. A. Khan, Design of Algorithmic State Machine Controlled Programmable Processor, Proceedings INMIC 2000, 2000, p 66-70.
Z. Suleman, S. A. Khan, I. Elahi and R. Khan, Hardware-Software Co-Simulation of Signal Processing and Communication, Proceedings INMIC 2000, 2000, p 114-118.
M. Mudassar Nisar and S. A. Khan, A Methodology for Designing And Verification of Digital Down Converter, Proceedings INMIC 2000, 2000, p 222-225.
Z. Ahmed and S. A. Khan, Development of Complex Architectures Using ERTL Language, Proceedings INMIC 2000, 2000, p 226-231.
S. A. Khan and M. Saqib, Parallel Viterbi Algorithm for a VLIW DSP, Proceedings IEEE ICASSP2000, Turkey
M. S. Sadiq and S. A. Khan, Scheduling and Mapping of Digital Signal Processing Algorithms on C6x DSP, Proceedings 33rd Asilomar Conference, 1999, USA 28. M. S. Sadiq and S. A. Khan, Optimal Digital Design and Implementation of CSD FIR Filters, in proceedings ICSPAT2000 USA.
M. S. Sadiq and S. A. Khan, Combined Scheduling and Mapping of Digital Signal Processing Algorithms on C6x DSP, in proceedings ICSPAT2000 USA.
M. S. Sadiq and S. A. Khan. Scheduling of Digital Signal Processing Algorithms on StarCore VLIW DSP, 14th International Conference on Parallel and Distributed Computing Systems (PDCS-2001), August 2001 Texas USA
Z. Ahmed and S. A. Khan, Design and Implementation of Complex Architectures using ERTL, in proceedings ICSPAT2000 USA.
M. Farooq, S. A. Khan, R. Khan and Z. Suleman, BURAQ: A DSP Development Framework, accepted for presentation in ICSPAT2000 USA
M. S. Sadiq and S. A. Khan, Scheduling of Digital Signal Processing Algorithms on StarCore VLIW DSP, in proceedings PDCS2001 USA
M. U. Ilyas and S. A. Khan, A Clustering Heuristic Algorithm For Scheduling Periodic And Deterministic Tasks On A Multiprocessor System, Proceedings INMIC 2001, 2001, p 1-5.
S. A. Khayam, S. A. Khan and M. S. Sadiq, A Generic Integer Programming Approach To Hardware/Software Co-Design, Proceedings INMIC 2001, 2001, p 6-9
Y. Rafiq, O. Bashir, S. I. Shah and S. A. Khan, FoIP Gateways - Architectures, Implementation and QoS Issues, Proceedings INMIC 2001, 2001, p 87-92
W. Latif, A. Shahid, F. Saud, S. Ali and S. A Khan, Exploring Multiple Levels Of Parallelism Using BOPs' DSP, Proceedings INMIC 2001, 2001, p 185-194
M. S. Sadiq and S. A. Khan, Optimal Scheduling and Mapping of Digital Signal Processing Algorithms on to VLIW DSPs, accepted with minor changes in EURASIP’s journal of “Applied Signal Processing”
O. Bashir, Y. Rafiq, I. Shah and S. A. Khan, Interworking real-time FoATM and FoIP, Proceedings INMIC 2002, Dec 2002
M. Z. Iqbal and S. A. Khan, A Multiple Path Constraint Quality of Service Routing Algorithm, Proceedings INMIC 2002, Dec 2002
S. A. Khan, S. Shah, F. Kashif and I. Zaman, A Low Complexity ITU-T Compliant DTMF Detector, Proceedings INMIC 2002, Dec 2002
Amjad, S. Khan, A. B. Mansoor and M. Hayat, Functional Verification of Multiprocessor based System-on-Chip on Distributed Systems, Proceedings INMIC 2002, Dec 2002
O. Mukhtar and S. A. Khan, FPGA based White Box Verification Methodology for SOC Design, Proceedings INMIC 2002, Dec 2002
A. Jawad, S. M. Masood, S. A. Khan and M. M. Rahamtullah, In-system Debug Support for a Processor Core, Proceedings INMIC 2002, Dec 2002
A. Abbas, S. Khan, H. Jamal and U. Farooq, An Optimal Application Specific Processor and Development Tools Design Methodology, Proceedings INMIC 2002, Dec 2002
D. Habib, S. A. Khan and S. Sadiq, Code Generation for Digital Communication Algorithms on Application-Specific Processors Proceedings of the 12th International Conference of WSE, July 27-31,2002, Canada
A. Abbas and S. A. Khan, BURAQ: A reconfiguable processor toolkit for VLIW architecture, in proceedings SPIE2002 USA, pp 4867-08
A. Abbas and S. A. Khan, A reconfigurable processor toolkit , in proceedings CATA2002, April 2002 USA
S. A. Khan, Silicon Real Time Operating System for Embedded DSPs accepted for publication 36 ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, Nov 2002 CA, USA
A. Abbas and S. A. Khan, Optimal generation of DSP processor from behavioral description, in proceedings FPL2002 Sep 2002, France
A. Abbas and S. A. Khan BPLD – Machine Description Language for Clustered VLIW Processors, in proceedings of System-on-Chip for real-time applications July 2002, Canada
A. Abbas and S. A. Khan, BURAQ: A re-configurable processor toolkit for VLIW architectures, 17th ISCA International Conference on Computers and Their Applications, vol. 1, pp. 156-159, April 2002.
A. Ghafoor, R. N. Iqbal and S. A. Khan, Modified Chamfer Matching Algorithm, in proc IDEAL 2003 Hong Kong pp 1102-1106, 2003
A.l Ghafoor, R. N. Iqbal and S. A. Khan, Image Matching Using Distance Transform. In proc. SCIA 2003: 654-660 July 2003, Halmstad, Sweden
A. Ghafoor, R. N. Iqbal and S. A. Khan, Stability Conditions for Discrete Domain Characteristic Polynomical, in proc SCI 2003, USA
A. Ghafoor, R. N. Iqbal and S. A. Khan, Robust Image Matching Algorithm, in proc. EC-VIP MC pp 155-160 July 2003, Zagreb Croatia
M. S. Sarfaraz and S. A. Khan, Multimedia Engineering in Video Encodings has been accepted for presentation in the International Workshop on Frontiers of Information Technology, December 23-24, 2003.
M. S. Sarfraz and S. A. Khan, A novel gradient based adaptive block-based motion estimation algorithm for low bit rate video coding IEEE SCONEST2003
M. S. Sarfraz and S. A. Khan. A Novel Gradient based very fast Adaptive Block-based Motion estimation algorithm for Low Bit rate video coding, ICICS Taiwan. pp 1213-1219, December, 2003.
A. Munawar, O. Qadir, M. Fahd Javed and S. A. Khan, Design And Implementation Of An Optimized Processor For Table Driven Solution & Its Application In Manet's (Mobile Adhoc Networks), in proc INMIC 2003
K. Jafri, N. Jafri and S. A. Khan, Modelling Temporal Partitioning In A Partially Reconfigurable System, in proc INMIC 2003
M. Abbas, B. Talha, S. A. Khan and A. Abbas, A Motion Estimation Chip For Block Based Mpeg-4 Video Application, in proc INMIC 2003
H. Jamal, F. Hameed, S. Saeed, M. Pasha and S. A. Khan, An RTL Verilog Processor, ICM2003 The 15th International Conference on Microelectronics Dec 2003 Cairo, Egypt
H. Jamal, K. Mahmood and S. A. Khan, An RTL Fast Hybrid Architecture ICM2003 The 15th International Conference on Microelectronics Dec 2003 Cairo, Egypt
M. S. Sarfraz and S. A. Khan Adaptive Block Matching Motion Estimation Algorithm For Video With Less Complex Motion Fields Hawaiin International Conference on Sciences, Jan. 2004 USA.
Z. H. Mir and S. A. Khan, A zone-based location service for mobile ad hoc networks, INCC 2004