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Progress
Updated On: Sep 29, 2009
# Milestone Deliverables Status
1 Completion of Algorithm Design Algorithms implemented in MATLAB Delivered
 
2 Transformation of Algorithm in Higher level language Fixed Point C Program Delivered
 
3 Completion of Top Level Architecture design and HW/SW distribution HW / SW Distributed Architecture Delivered
4 Completion of Hardware design for targeted FPGA Hardware implementation in Verilog HDL Verilog Implementation in Progress
5 Verification and Synthesis of Verilog Code for targeted FPGA Verified netlist for FPGA NA
6 Completion of Co-verification HW/SW integrated verified design NA
7 Compilation of results and archiving of the project documents Review of results and documentation NA